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 HD26LS31
Quadruple Differential Line Drivers With 3 State Outputs
REJ03D0294-0200Z (Previous ADE-205-576 (Z)) Rev.2.00 Jul.16.2004
Description
The HD26LS31 features quadruple differential line drivers which satisfy the requirements of EIA standard RS-422A. This device is designed to provide differential signals with high current capability on bus lines. The circuit provides enable input to control all four drivers. The output circuit has active pull up and pull down and is capable of sinking or sourcing 40 mA.
Features
* Ordering Information
Part Name HD26LS31P Package Type DILP-16 pin Package Code DP-16E, -16FV P Package Abbreviation -- Taping Abbreviation (Quantity)
Logic Diagram
1A 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z
2A
3A 4A Enable G Enable G
Rev.2.00, Jul.16.2004, page 1 of 11
HD26LS31
Pin Arrangement
1A 1 1Y 2 1Z 3 Enable G 4 2Z 5 2Y 6 2A 7 GND 8
16 VCC 15 4A 14 4Y 13 4Z 12 Enable G 11 3Z 10 3Y 9 3A
(Top view)
Function Table
Input A H L H L X H L X Z : : : : H H X X L High level Low level Irrelevant High impedance (Off) Enables G X X L L H G H L H L Z Outputs Y L H L H Z Z
Absolute Maximum Ratings
Item Supply Voltage Input Voltage Output Voltage Power Dissipation Storage Temperature Range VCC VIN VOUT PT Topr Symbol 7.0 7.0 5.5 1 0 to +70 Ratings V V V W C Unit
Lead Temperature Range Tstg -65 to +150 C Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply Voltage Output Current Output Current Operating Temperature Symbol VCC IOH IOL Topr Min 4.75 -- -- 0 Typ 5.0 -- -- 25 Max 5.25 -40 40 70 Unit V mA mA -- VCC All Output All Output -- Application Terminal
Rev.2.00, Jul.16.2004, page 2 of 11
HD26LS31
Electrical Characteristics (Ta = 0 to +70C)
Item Input Voltage Symbol VIH VIL Min Typ*1 Max 2.0 -- -- 2.5 -- -- -- -- -- -- -- -30 -- -- -- -- -- -- -- -- -- -- -- -- -- 32 -- 0.8 -1.5 -- 2.4 0.5 -20 20 0.1 20 mA mA A All Inputs VCC = 5.25 V VCC = 5.25 V VCC = 5.25 V Unit V Application Terminal All Inputs VCC = 4.75 V, II = -18 mA VCC = 4.75 V IOH = -20 mA IOH = -40 mA IOL = 40 mA VO = 0.5 V VO = 2.5 V VI = 7 V VI = 2.7 V VI = 0.4 V All Outputs VCC VCC = 5.25 V VCC = 5.25 V Conditions
Input Clamp Voltage VIK Output Voltage VOH VOH VOL Output Current Input Current IOZL IOZH II IIH
All Outputs
IIL Short Circuit Output IOS*2 Current Supply Current ICC
-0.36 mA -150 80
Notes: 1. All typical values are at VCC = 5 V, Ta = 25C 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
Switching Characteristics (VCC = 5 V, Ta = 25C)
Item Propagation Delay Time Output Enable Time Output Disable Time Complementary Output To Output Symbol Min Typ Max Unit tPLH tPHL tZH tZL tHZ tLZ Skew -- -- -- -- -- -- -- 14 14 25 37 21 23 1 20 20 40 45 30 35 6 ns ns ns ns ns ns ns Application terminal All Outputs Test circuit 1 2 3 2 3 1 CL = 30 pF CL = 30 pF, RL 75 = CL = 30 pF, RL 180 = CL = 10 pF CL = 10 pF CL = 30 pF Conditions
Rev.2.00, Jul.16.2004, page 3 of 11
HD26LS31 Test Circuit 1
4.5 V
G Input Pulse Generator PRR = 1MHz Duty Cycle 50% Zout = 50 G Z Y Output CL = 30 pF CL = 30 pF Output
A
Note:
1. CL includes probe and jig capacitance.
Waveforms
tr Input 0.3 V t PLH Output Y 2.7 V 1.3 V 2.7 V 1.3 V 0.3 V t PHL VOH 1.5 V Skew t PHL 1.5 V t PLH VOH Output Z 1.5 V VOL 1.5 V Skew VOL tf 3V 0V
Rev.2.00, Jul.16.2004, page 4 of 11
HD26LS31 Test Circuit 2
VCC 4.5 V Output 180 S1 75
A Input Pulse Generator PRR = 1 MHz Duty Cycle 50% Zout = 50
Y Z
CL Output
G G CL S1 75
180
Note:
1. CL includes probe and jig capacitance.
Waveforms
tr Enable G 0.3 V 2.7 V 1.5 V 2.7 V 1.5 V 0.3 V tf 3V 0V
Enable G
S1 : Open t ZH
S1 : Closed t HZ VOH 1.5 V 0V
Output S1 Open
1.5 V
0.5 V
Rev.2.00, Jul.16.2004, page 5 of 11
HD26LS31 Test Circuit 3
4.5 V Output 180 A Input Pulse Generator PRR = 1 MHz Duty Cycle 50% Zout = 50 Y Z G 180 G CL 75 S2 CL Output 75 S2 VCC
Note:
1. CL includes probe and jig capacitance.
Waveforms
tr Enable G 0.3 V 2.7 V 1.5 V 2.7 V 1.5 V 0.3 V tf 3V 0V
Enable G
S2 : Open t ZL
S2 : Closed t LZ 4.5 V 1.5 V 0.5 V VOL
Output
1.5 V
Rev.2.00, Jul.16.2004, page 6 of 11
HD26LS31
HD26LS31 Line Driver Applications
The HD26LS31 is a line driver that meets the EIA RS-422A conditions, and has been designed to supply a high current for differential signals to a bus line. Its features are listed below. * * * * * Operates on a single 5 V power supply. High output impedance when power is off Three-state output On-chip current limiter circuit Sink current and source current both 40 mA
A block diagram is shown in figure 1. The enable function is common to all four drivers, and either active-high or active-low can be selected. The output section consists of two output stages (the Y side and Z side), each of which has the same sink current and source current capacity. Input is TTL compatible, and an output current limiter circuit is built into the output stage as shown in figure 2.
1A 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z
2A
3A 4A Enable G Enable G
Figure 1 HD26LS31 Block Diagram The output current limiter circuit consists of transistor Q1 and resistance R1, and operates when the voltage drop on both sides of R1 reaches approximately 0.7 V. At this time the current, i, is as follows: i = 0.7 (V) / 9 () 78 (mA) When a current greater than this flows, Q1 is turned on, the Q2 base current flows to the output side, and the flow of an excessively large output current is prevented. However, since this type of current limiter circuit has the characteristics shown in figure 3, the output stage power dissipation is large. Therefore, when the output is shorted, this should be limited to a maximum of one second for one pin only. The IOL vs. VOL characteristic for low-level output is shown in figure 4. An example of termination resistance connection when the HD26LS31 is used as a balanced differential type driver is shown.
VCC Q2 Q3 Q1 R1 9 Output Q4
Figure 2 Output Stage Circuit Configuration
Rev.2.00, Jul.16.2004, page 7 of 11
HD26LS31 When termination resistance RT is connected between the two transmission lines, as shown in figure 7 the current path situation is that current IOH on the side outputting a high level (in this case, the Y output) flows to the side outputting a low level (in this case, the Z output) via RT, with the result that the low level rise is large. If termination resistance RT is dropped to GND on both transmit lines, as shown in figure 5 the current path situation is that the current that flows into the side outputting a low level (in this case, the Z output) is only the input bias current from the receiver. As this input bias current is small compared with the signal current, it has almost no effect on the differential input signal at the receiver end. Figure 6 shows the output voltage characteristics when termination resistance RT is varied. Also, when used in a party line system, etc., the low level rises further due to the receiver input bias current, so that it is probably advisable to drop the termination resistance to GND. However, the fact that it is possible to make the value of RT equal to the characteristic impedance of the transmission line offers the advantage of being able to hold the power dissipation on the side outputting a high level to a lower level than in the above case. Consequently, the appropriate use must be decided according to the actual operating conditions (transmission line characteristics, transmission distance, whether a party line is used, etc.). Figure 8 shows the output voltage characteristics when termination resistance RT is varied.
5.0 VCC = 5.0 V
VC = C 5.25 VC = C 4.75 V
Output Voltage VOH (V)
4.0
Ta = 25C
3.0
V
2.0
1.0
0
-20
-40
-60
-80
-100
Output Current IOH (mA)
Figure 3 IOH vs. VOH Characteristics
0.5 Ta = 25C VCC = 4.75 V VCC = 5.0 V VCC = 5.25 V
Output Voltage VOL (V)
0.4
0.3
0.2
0.1
0
10
20
30
40
50
Output Current IOL (mA)
Figure 4 IOL vs. VOL Characteristics
Rev.2.00, Jul.16.2004, page 8 of 11
HD26LS31
"H" IOH RT RT IIN (Receiver)
Y
"L" Z
Z RT = O 2 ZO is the transmission line characteristic impedance
Figure 5 Example of Driver Use-1
Output Voltage VOH (Y), VOL (Z) (V)
5 2 1.0 0.5 "H" 0.2 0.1 0.05 10 RT VOL (Z) Z GND 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 50 k Termination Resistance RT () VOL VOH Y RT VCC = 5 V Ta = 25C VOH (Y)
Figure 6 Termination Resistance vs. Output Voltage Characteristics
Y "H" IOH
RT "L" Z IOL IIN (Receiver)
RT = ZO ZO is the transmission line characteristic impedance
Figure 7 Example of Driver Use-2
Rev.2.00, Jul.16.2004, page 9 of 11
HD26LS31 A feature of termination implemented as shown in figure 9 is that power dissipation is low when the duty of the transmitted signal is high. However, care is required, since if RT is sufficiently small, when the output on the pulled-up side goes low, since the inverter transistor (Q4 in figure 2) has no protection circuit, and so a large current will flow and the output low level will rise. Figure 10 shows the output voltage characteristics when termination resistance RT is varied. With the method of using the driver described above, if termination resistance RT becomes sufficiently small, the region within which the output current limiter circuit operates will be entered, as can be seen from the IOH vs. VOH characteristics shown in figure 3. In this region, the output stage power dissipation is large and the output voltage changes abruptly. A measure such as insertion of a capacitor in series with the termination resistance is therefore necessary. Consequently, when selecting the transmission line, the circuit termination resistance to be used requires careful consideration.
Output Voltage VOH (Y), VOL (Z) (V)
5 VOH (Y) 2 1.0 0.5 0.2 0.1 Z 0.05 10 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k Termination Resistance RT () 50 k GND VOL VOL (Z) Y "H" RT VOH VCC = 5 V Ta = 25C
Figure 8 Termination Resistance vs. Output Voltage Characteristics
VCC Y Data input RT
Z
RT
Figure 9 Example of Driver Use-3
Output Voltage VOH (Y), VOL (Z) (V)
5 VOH (Z) 2 1.0 0.5 "L" 0.2 0.1 0.05 10 VOL (Y) Z RT GND VOH VOL Y RT VCC VCC = 5 V Ta = 25C
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k Termination Resistance RT ()
50 k
Figure 10 Termination Resistance vs. Output Voltage Characteristic
Rev.2.00, Jul.16.2004, page 10 of 11
HD26LS31
Package Dimensions
As of January, 2003
Unit: mm 19.2 20.32 Max
16
9
6.3 7.4 Max
1
0.89 1.3
8
2.54 Min 5.06 Max
7.62
0.51 Min
2.54 0.25
0.48 0.1
0.25 - 0.05 0 - 15
Package Code JEDEC JEITA Mass (reference value) DP-16E Conforms Conforms 1.05 g
+ 0.1
Unit: mm 19.2 20.32 Max
16
9
6.3 7.4 Max
1
0.89 1.3
8
2.54 Min 5.06 Max
7.62
0.51 Min
2.54 0.25
*0.48 0.08
*0.25 0.06 0 - 15
Package Code JEDEC JEITA Mass (reference value) DP-16FV Conforms Conforms 1.05 g
*NI/Pd/AU Plating
Rev.2.00, Jul.16.2004, page 11 of 11
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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